1. Field of the Invention
The present invention relates generally to an apparatus and method for receiving signals in a communication system, and in particular, to an apparatus and method for receiving signals using a different quantization scheme according to the number of quantization bits in a communication system using a Low Density Parity Check (LDPC) code.
2. Description of the Related Art
The next generation communication system has evolved into a packet service communication system, which is a system for transmitting burst packet data to a plurality of mobile stations (MSs) and is suitable for high-capacity data transmission. It is also known that the next generation communication system, together with a turbo code as a channel code, has high performance gain during high-speed data transmission, and the system actively considers using the LDPC code that can increase data transmission reliability by efficiently correcting errors caused by noises generated in a transmission channel. The next generation communication systems that are actively considering the use of the LDPC code include an Institute of Electrical and Electronics Engineers (IEEE) 802.16e communication system and an IEEE 802.11n communication system.
FIG. 1 is a schematic diagram illustrating a structure of a signal transmission apparatus in a general communication system using an LDPC code.
Referring to FIG. 1, the signal transmission apparatus includes an encoder 111, a modulator 113, and a transmitter 115. If an information vector s that the signal transmission apparatus intends to transmit is generated, the information vector s is delivered to the encoder 111. The encoder 111 encodes the information vector s into a codeword vector c, i.e. LDPC codeword, using a predetermined coding scheme, and outputs the codeword vector c to the modulator 113. Herein, the coding scheme can be an LDPC coding scheme. The modulator 113 modulates the codeword vector c into a modulation vector m using a predetermined modulation scheme, and outputs the modulation vector m to the transmitter 115. The transmitter 115 performs transmission signal processing on the modulation vector m output from the modulator 113, and transmits the resulting signal to a signal reception apparatus via an antenna ANT.
FIG. 2 is a schematic diagram illustrating a structure of a signal reception apparatus in a general communication system using an LDPC code.
Here, the signal reception apparatus includes a receiver 211, a demodulator 213, and a decoder 215. A signal transmitted by a signal transmission apparatus is received at the signal reception apparatus via an antenna ANT, and the received signal is delivered to the receiver 211. The receiver 211 then performs signal reception processing on the received signal, and outputs the reception-processed received vector r to the demodulator 213. The demodulator 213 demodulates the received vector r output from the receiver 211 into a demodulation vector x using a demodulation scheme corresponding to the modulation scheme used in the modulator 113 of the signal transmission apparatus, and outputs the demodulation vector x to the decoder 215. The decoder 215 decodes the demodulation vector x output from the demodulator 213 using a decoding scheme corresponding to the coding scheme used in the encoder 111 of the signal transmission apparatus, and finally outputs the decoded signal as a restored information vector
            s      _        ^    .
The LDPC code is defined by a parity check matrix in which major elements have a value of 0 and minor elements, other than the elements having a value of 0 have a non-zero value, for example, have a value of 1. The LDPC code can be expressed with a bipartite graph, and the bipartite graph is expressed with variable nodes, check nodes, and edges for connecting the variable nodes to the check nodes.
The LDPC code can be decoded using an iterative decoding algorithm based on the sum-product algorithm in the bipartite graph. The sum-product algorithm is a kind of a message passing algorithm, which is an algorithm that exchanges messages through edges in the bipartite graph and updates the messages by calculating output messages from the messages input to the variable nodes or the check nodes. Therefore, a decoder for decoding the LDPC code, because it uses an iterative decoding algorithm based on the sum-product algorithm, has lower complexity than that of a decoder for the turbo code and can be easily implemented with a parallel processing decoder.
A probability mass function for a binary random variable can be expressed in a Log Likelihood Ratio (LLR) as shown in Equation (1):
                    log        ⁢                                  ⁢                              p            0                                p            1                                              (        1        )            where p0 denotes probability that a bit value will be 0, and p1 denotes probability that a bit value will be 1.
When iterative decoding is performed on the LLR input shown in Equation (1) in the bipartite graph using the sum-product algorithm, a message update rule during ith iteration (i.e. ith iterative decoding) is as follows:
Message Update Rule during ith Iteration
                              (          1          )                ⁢                                  ⁢        Initialization                                          E                      n            ,            m                                (            0            )                          =        0                                          (          2          )                ⁢                                  ⁢        Variable        ⁢                                  ⁢        Node        ⁢                                  ⁢        Update        ⁢                                  ⁢        Rule                                          T                      n            ,            m                                (            i            )                          =                              I            n                    +                                    ∑                                                m                  ′                                ∈                                                      M                    ⁡                                          (                      n                      )                                                        ⁢                  \                  ⁢                  m                                                      ⁢                          E                              n                ,                                  m                  ′                                                            (                                  i                  -                  1                                )                                                                                      (          3          )                ⁢                                  ⁢        Check        ⁢                                  ⁢        Node        ⁢                                  ⁢        Update        ⁢                                  ⁢        Rule                                          E                      n            ,            m                                (            i            )                          =                              ∏                                          n                ′                            ∈                                                N                  ⁡                                      (                    m                    )                                                  ⁢                \                ⁢                                                                  ⁢                n                                              ⁢                      sign            ⁢                                                  ⁢                          (                              T                                                      n                    ′                                    ,                  m                                                  (                  i                  )                                            )                        ×                                          f                                  -                  1                                            [                                                ∑                                                            n                      ′                                        ∈                                                                  N                        ⁡                                                  (                          m                          )                                                                    ⁢                      \                      ⁢                                                                                          ⁢                      n                                                                      ⁢                                  f                  ⁡                                      (                                                                                        T                                                                              n                            ′                                                    ,                          m                                                                          (                          i                          )                                                                                                            )                                                              ]                                                                        (          4          )                ⁢                                  ⁢        Final        ⁢                                  ⁢        Node        ⁢                                  ⁢        Update        ⁢                                  ⁢        Rule                                          T          n                =                              I            n                    +                                    ∑                              m                ∈                                  M                  ⁡                                      (                    n                    )                                                                        ⁢                          E                              n                ,                m                                            (                                  i                  -                  1                                )                                                        
In the ‘message update rule during ith iteration’, Tn,m(i) denotes a message delivered from an nth variable node to an mth check node during ith iteration, En,m(i) denotes a message delivered from an mth check node to an nth variable node during ith iteration, In denotes an LLR of a channel received at an nth variable node, M(n) denotes a set of all check nodes connected to an nth variable node, M(n)\m denotes a set excluding an mth check node from M(n), N(m) denotes a set of all variable nodes connected to an mth check node, and N(m)\n denotes a set excluding an nth variable node from N(m). In addition, sign(x) denotes a function indicating a sign of ‘x’, and this function has a value of 1 for x=‘positive number’ and a value of −1 for x=‘negative number’.
In the ‘message update rule during ith iteration’, the check node update rule is expressed as a product of a sign and a magnitude, where the sign is denoted by
      ∏                  n        ′            ∈                        N          ⁡                      (            m            )                          ⁢        \        ⁢                                  ⁢        n              ⁢      sign    ⁢                  ⁢          (              T                              n            ′                    ,          m                          (          i          )                    )      and the magnitude is denoted by
            f              -        1              [                  ∑                              n            ′                    ∈                                    N              ⁡                              (                m                )                                      ⁢            \            ⁢                                                  ⁢            n                              ⁢              f        ⁡                  (                                                T                                                n                  ′                                ,                m                                            (                i                )                                                          )                      ]    .In addition, the function f(x) can be expressed as Equation (2):
                              f          ⁡                      (            x            )                          =                                            -              ln                        ⁢                                                  ⁢                          (                              tanh                ⁡                                  (                                      x                    2                                    )                                            )                                =                      ln            ⁢                                                  ⁢                                                            ⅇ                  x                                +                1                                                              ⅇ                  x                                -                1                                                                        (        2        )            
In Equation (2), a relationship of f−1(x)=f(x) is satisfied.
In order to actually implement a decoder for decoding the LDPC code with digital hardware, all messages which are input and output to/from the decoder should be expressed with quantized values. Therefore, the decoder includes a quantizer for quantizing the messages, a check node processor for performing message processing at a check node, and a variable node processor for performing message processing at a variable node. The quantizer can quantize messages using either a uniform quantization scheme or a non-uniform quantization scheme. A quantizer that quantizes messages using the uniform quantization scheme will be referred to as a “uniform quantizer,” and a quantizer that quantizes messages using the non-uniform quantization scheme will be referred to as a “non-uniform quantizer.” In addition, when the messages are quantized, an interval of the quantization will be referred to as “quantization interval.” Therefore, the uniform quantizer quantizes messages at uniform quantization intervals, and the non-uniform quantizer quantizes messages at non-uniform quantization intervals.
As described above, the decoder includes a quantizer, a check node processor, and a variable node processor. The quantizer is implemented with a uniform quantizer or a non-uniform quantizer according to a quantization scheme determined by the decoder to use. The check node processor and the variable node processor are implemented and are to be optimized for the quantizer. For example, if the quantizer is a uniform quantizer, the check node processor and the variable node processor are implemented and are to be optimized for the uniform quantizer, and if the quantizer is a non-uniform quantizer, the check node processor and the variable node processor are implemented and are to be optimized for the non-uniform quantizer.
However, the decoder generally includes only one quantizer. That is, the decoder includes only a selected one of the uniform quantizer and the non-uniform quantizer, and includes a check node processor and a variable node processor optimized for the included quantizer. The decoder cannot decode an LDPC code using a different quantization scheme according to the number of quantization bits, because it is implemented in such a way of determining any one quantization scheme as its quantization scheme and then optimizing a check node processor and a variable node processor for the determined quantizer.